Rev. 1.0 / Nov. 2009

24

H5DU5162ETR

Note:

1. All voltages referenced to Vss.

2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,

but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to

be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production

tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.

Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec-

tronics).

4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to

VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under

normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).

5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result

of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the

dc input LOW (HIGH) level.

6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is

recognized as LOW.

7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference

level for signals other than CK, /CK is VREF.

8. The output timing reference voltage level is VTT.

9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must

be powered down and then restarted through the specified initialization sequence before normal operation can continue.

10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to

a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but

system performance (bus turnaround) will degrade accordingly.

12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A

valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previ-

ously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could

be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

14. For command/address input slew rate ≥ 1.0 V/ns.

15. For command/address input slew rate ≥ 0.5 V/ns and ＜ 1.0 V/ns

16. For CK & /CK slew rate ≥ 1.0 V/ns (single-ended)

17. These parameters guarantee device timing, but they are not necessarily tested on each device.

They may be guaranteed by device design or tester correlation.

18. Slew Rate is measured between VOH(ac) and VOL(ac).

19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half

period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.

Figure: Timing Reference Load

VDDQ

50

Output

(VOUT)

30 pF

Ω