Rev. 1.0 / Nov. 2009

15

H5DU5162ETR

CAS LATENCY

The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the

availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for DDR266/333 or 3

clocks for DDR400 product.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident

with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-

ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically

disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any

time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally

applied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver

option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will

reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver

and the half strength driver are included in this document.