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H5DU5182EFR-FAC Datasheet(PDF) 19 Page - Hynix Semiconductor

Part # H5DU5182EFR-FAC
Description  512Mb DDR SDRAM
Download  30 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5DU5182EFR-FAC Datasheet(HTML) 19 Page - Hynix Semiconductor

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Rev. 1.0 / Nov. 2009
19
1H5DU5182EFR
H5DU5162EFR
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1: Operating current: One bank operation
1. Typical Case: VDD = 2.5V, T=25 oC for DDR200, 266, 333; VDD = 2.6V, T=25 oC for DDR400
2. Worst Case: VDD = 2.7V, T= 0 oC
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=2, tRCD = 2*tCK, tRC = 10*tCK, tRAS = 5*tCK
Read: A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK
Read: A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR400(200Mhz, CL=3): tCK = 5ns, CL=3, BL=4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK
Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
50% of data changing at every burst
Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7: Operating current: Four bank operation
1. Typical Case: VDD = 2.5V, T=25 oC for DDR200, 266, 333; VDD = 2.6V, T=25 oC for DDR400
2. Worst Case: VDD = 2.7V, T= 0 oC
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with Autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR400(200Mhz, CL=3): tCK = 5ns, CL = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP


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