H5PS5162FFR-C datasheet(36/39 Pages) HYNIX

Part #	H5PS5162FFR-C

Description	512Mb DDR2 SDRAM

PDF	39 Pages

Scroll/Zoom	100%

Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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36 / 39 page

Rev. 1.0 / July. 2008

36

Release

H5PS5162FFR series

36. These parameters are specified per their average values, however it is understood that the following

relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and

max of SPEC values are to be used for calculations in the table below.)

Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps

37. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but

not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing

tQH.

The value to be used for tQH calculation is determined by the following equation;

tHP = Min ( tCH(abs), tCL(abs) ),

where,

tCH(abs) is the minimum of the actual instantaneous clock HIGH time;

tCL(abs) is the minimum of the actual instantaneous clock LOW time;

Parameter

Symbol

DDR2-667

DDR2-800

Units

Notes

min

max

min

max

Clock period jitter

tJIT(per)

-125

125

-100

100

ps

35

Clock period jitter during DLL locking period

tJIT(per,lck)

-100

100

-80

80

ps

35

Cycle to cycle clock period jitter

tJIT(cc)

-250

250

-200

200

ps

35

Cycle to cycle clock period jitter during DLL

locking period

tJIT(cc,lck)

-200

200

-160

160

ps

35

Cumulative error across 2 cycles

tERR(2per)

-175

175

-150

150

ps

35

Cumulative error across 3 cycles

tERR(3per)

-225

225

-175

175

ps

35

Cumulative error across 4 cycles

tERR(4per)

-250

250

-200

200

ps

35

Cumulative error across 5 cycles

tERR(5per)

-250

250

-200

200

ps

35

Cumulative error across n cycles,

n=6...10, inclusive

tERR(6~10per)

-350

350

-300

300

ps

35

Cumulative error across n cycles,

n=11...50, inclusive

tERR(11~50per)

-450

450

-450

450

ps

35

Duty cycle jitter

tJIT(duty)

-125

125

-100

100

ps

35

Parameter

Symbol

min

max

Units

Absolute clock period

tCK(abs)

tCK(avg),min+tJIT(per),min

tCK(avg),max+tJIT(per),max

ps

Absolute clock HIGH pulse width

tCH(abs)

tCH(avg),min*tCK(avg),min+tJIT(

per),min

tCH(avg),max*tCK(avg),max+tJI

T(per),max

ps

Absolute clock LOW pulse width

tCL(abs)

tCL(avg),min*tCK(avg),min+tJIT(

per),min

tCL(avg),max*tCK(avg),max+tJIT

(per),max

ps

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