Rev. 1.0 / July. 2008

34

Release

H5PS5162FFR series

24. tWTR is at least two clocks (2 x tCK or 2 x nCK) independent of operation frequency.

25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the

input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of

its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended

data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under

test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the

input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of

its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended

data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under

test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE

must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus,

after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK

+ tIH.

DQS

tDH

tDS

DQS

tDH

tDS

Differential Input waveform timing