Rev. 1.0 / July. 2008

32

Release

H5PS5162FFR series

1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the

datasheet value to the derating value listed in above Table.

Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere

to dc level is used for derating value(see Fig b.)

Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

d.)

Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached

For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value

for this parameter, but system performance (bus turnaround) will degrade accordingly.

11. MIN ( t CL, t CH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as

provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH).

For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock

source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.

12. t QH = t HP – t QHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH,tCL).

tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the

next transition, both of which are, separately, due to data pin skew and output pattern effects, and

p-channel to n-channel variation of the output drivers.

13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the

output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given

cycle.

14. t DAL = (nWR) + ( tRP/tCK):

For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the

application clock period. nWR refers to the t WR parameter stored in the MR.

Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns)

clocks =4 +(4)clocks=8clocks.