22

IRTX

IRRX1

IRSL0

PC97/87338VJG

63

65

66

PC87308VUL

81

80

79

PC87108AVHG

39

38

37

PC87109VBE

15

16

14

Please refer to the National Semiconductor data sheets and application notes for updated information.

(B) HSDL-3602 Interoperability with National Semiconduc-

tor PC97338VJG SIO Evaluation R eport

Introduction

The objective of this report is to demonstrate the in-

teroperability of the HSDL-3602 IR transceiver IR mod-

ule as wireless communication ports at the speed of 2.4

kb/s - 4 Mb/s with NS’s PC97338VJG Super I/O under

typical operating conditions.

Test Procedures

(1)

Two PC97338VJG evaluation boards were con-

nected to the ISA Bus of two PCs (Pentium 200

MHz) running Microsoft’s DOS operating system.

One system with an HSDL-3602 IR transceiver

connected to the PC97338VJG evaluation board

will act as the master device. Another system with

an HSDL-3602 IR transceiver connected to the

PC97338VJG will act as the slave device (i.e. De-

vice Under Test).

(2)

The test software used in this interoperability test

is provided by National Semiconductor. A file size

of 1.7M byte from the master device, with the

PC97338VJG performing the framing, encoding is

transmitted to the slave device. The slave device,

with the PC97338VJG performing the decoding,

and CRC checksum, will receive the file. The file is

then checked for error by comparing the received

file with the original file using the DOS “fc” com-

mand.

(3)

The link distance is measured by adjusting the dis-

tance between the master and slave for errorless

data communications.

TXD (9)

MD0 (4)

MD1 (5)

RXD (8)

FIR_SEL (3)

GND (7)

AGND (2)

LEDA (10)

R1

SP

HSDL-3602

CX1

CX2

NATIONAL

SEMICONDUCTOR

SUPER I/O

OR

IR CONTROLLER

IRTX

IRRX1

IRSL0

HSDL-3602 FUNCTIONAL DIAGRAM (A)

*

*

* MODE GROUND FOR

FULL POWER OPERATION

HSDL-3600

FUNCTIONAL BLOCK DIAGRAM