MAX16068 datasheet(33/40 Pages) MAXIM

Part #	MAX16068

Description	6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

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Manufacturer	MAXIM [Maxim Integrated Products]

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______________________________________________________________________________________ 33

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Exit1-IR: A rising edge on TCK with TMS low puts the

controller in the pause-IR state. If TMS is high on the ris-

ing edge of TCK, the controller enters the update-IR state.

Pause-IR: Shifting of the instruction shift register halts

temporarily. With TMS high, a rising edge on TCK puts

the controller in the exit2-IR state. The controller remains

in the pause-IR state if TMS is low during a rising edge

on TCK.

Exit2-IR: A rising edge on TCK with TMS high puts the

controller in the update-IR state. The controller loops

back to shift-IR if TMS is low during a rising edge of TCK

in this state.

Update-IR: The instruction code that has been shifted

into the instruction shift register latches to the parallel

outputs of the instruction register on the falling edge of

TCK as the controller enters this state. Once latched,

this instruction becomes the current instruction. A rising

edge on TCK with TMS low puts the controller in the run-

test/idle state. With TMS high, the controller enters the

select-DR-scan state.

Instruction Register

The instruction register contains a shift register as well

as a latched 5-bit wide parallel output. When the TAP

controller enters the shift-IR state, the instruction shift

register connects between TDI and TDO. While in the

shift-IR state, a rising edge on TCK with TMS low shifts

the data one stage toward the serial output at TDO. A

rising edge on TCK in the exit1-IR state or the exit2-IR

state with TMS high moves the controller to the update-

IR state. The falling edge of that same TCK latches the

data in the instruction shift register to the instruction

register parallel output. Table 21 shows the instructions

supported by the MAX16068 and the respective opera-

tional binary codes.

BYPASS: When the BYPASS instruction is latched into

the instruction register, TDI connects to TDO through the

1-bit bypass test data register. This allows data to pass

from TDI to TDO without affecting the device’s operation.

IDCODE: When the IDCODE instruction is latched into

the parallel instruction register, the identification data

register is selected. The device identification code is

loaded into the identification data register on the rising

edge of TCK following entry into the capture-DR state.

Shift-DR can be used to shift the identification code

out serially through TDO. During test-logic-reset, the

IDCODE instruction is forced into the instruction register.

The identification code always has a ‘1’ in the LSB posi-

tion. The next 11 bits identify the manufacturer’s JEDEC

number and number of continuation bytes followed by

16 bits for the device and 4 bits for the version. See

Table 22.

Table 21. JTAG Instruction Set

Table 22. 32-Bit Identification Code

INSTRUCTION

CODE

NOTES

BYPASS

0x1F

Mandatory instruction code

IDCODE

0x00

Load manufacturer ID code/part number

USERCODE

0x03

Load user code

LOAD ADDRESS

0x04

Load address register content

READ DATA

0x05

Read data pointed by current address

WRITE DATA

0x06

Write data pointed by current address

REBOOT

0x07

Reboot FLASH data content into register file

SAVE

0x08

Trigger emergency save to flash

SETFLSHADD

0x09

Flash page access ON

RSTFLSHADD

0x0A

Flash page access OFF

SETUSRFLSH

0x0B

User flash access ON (must be in flash page already)

RSTUSRFLSH

0x0C

User flash access OFF (return to flash page)

MSB

LSB

VERSION (4 BITS)

PART NUMBER (16 BITS)

MANUFACTURER (11 BITS)

FIXED VALUE (1 BIT)

0001

1000000000000010

00011001011

1

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