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MAX16068 Datasheet(PDF) 31 Page - Maxim Integrated Products |
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MAX16068 Datasheet(HTML) 31 Page - Maxim Integrated Products |
31 / 40 page ![]() ______________________________________________________________________________________ 31 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers When PEC is enabled, the Block Read protocol becomes: 1) The master sends a START condition. 2) The master sends the 7-bit slave ID plus a write bit (low). 3) The addressed slave asserts an ACK on the data line. 4 The master sends 8 bits of the block read command code. 5) The slave asserts an ACK on the data line unless busy. 6) The master sends a REPEATED START condition. 7) The master sends the 7-bit slave ID plus a read bit (high). 8) The slave asserts an ACK on the data line. 9) The slave sends 8-bit byte count (16). 10) The master asserts an ACK on the data line. 11) The slave sends 8 bits of data. 12) The master asserts an ACK on the data line. 13) Repeat 11 and 12 up to 15 times. 14) The slave sends an 8-bit PEC byte. 15) The master asserts a NACK on the data line. 16) The master generates a STOP condition. SMBALERT (ALERT) The MAX16068 supports the SMBus alert protocol. To enable the SMBus alert output, set r40h[4] to ‘1’, then configure GPIO1 to act as the SMBus alert (ALERT) according to Table 12. This output is open drain and uses the wired-OR configuration with other devices on the SMBus. During a fault, the MAX16068 asserts ALERT low, signaling the master that an interrupt has occurred. The master responds by sending the ARA (Alert Response Address) protocol on the SMBus. This protocol is a read byte with 09h as the slave address. The slave acknowledges the ARA (09h) address and sends its own SMBus address to the master. The slave then deasserts ALERT. The master can then query the slave and determine the cause of the fault. By checking r1C[7], the master can confirm that the MAX16068 trig- gered the SMBus alert. The master must send the ARA before clearing r1Ch[7]. Clear r1Ch[7] by writing a ‘1’. If GPIO1 is configured as the SMBus alert output but the SMBus alert feature is disabled (r40h[4] is set to ‘0’), GPIO1 acts as an additional fault output. JTAG Serial Interface The MAX16068 features a JTAG port that complies with a subset of the IEEE 1149.1 specification. Either the SMBus or the JTAG interface can be used to access internal memory; however, only one interface is allowed to run at a time. The MAX16068 contains extra JTAG instructions and registers not included in the JTAG specification that provide access to internal memory. The extra instructions include LOAD ADDRESS, WRITE, READ, REBOOT, and SAVE. Test Access Port (TAP) Controller State Machine The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK. See Figure 11 for a diagram of the finite state machine. The possible states are described as follows: Test-Logic-Reset: At power-up, the TAP controller is in the test-logic-reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. This state can be reached from any state by driving TMS high for five clock cycles. Run-Test/Idle: The run-test/idle state is used between scan operations or during specific tests. The instruction register and test data registers remain idle. Select-DR-Scan: All test data registers retain their previ- ous state. With TMS low, a rising edge of TCK moves the controller into the capture-DR state and initiates a scan sequence. TMS high during a rising edge on TCK moves the controller to the select-IR-scan state. Capture-DR: Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. On the rising edge of TCK, the controller goes to the shift-DR state if TMS is low or it goes to the exit1-DR state if TMS is high. Shift-DR: The test data register selected by the current instruction connects between TDI and TDO and shifts data one stage toward its serial output on each rising edge of TCK while TMS is low. On the rising edge of TCK, the controller goes to the exit1-DR state if TMS is high. Exit1-DR: While in this state, a rising edge on TCK puts the controller in the update-DR state. A rising edge on TCK with TMS low puts the controller in the pause-DR state. |
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