MAX16067 datasheet(40/47 Pages) MAXIM

Part #	MAX16067

Description	6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

PDF	47 Pages

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Manufacturer	MAXIM [Maxim Integrated Products]

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40 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Table 29. 32-Bit Identification Code

Table 30. 32-Bit User-Code Data

BYPASS: When the BYPASS instruction is latched into

the instruction register, TDI connects to TDO through the

1-bit bypass test data register. This allows data to pass

from TDI to TDO without affecting the device’s operation.

IDCODE: When the IDCODE instruction is latched into

the parallel instruction register, the identification data

register is selected. The device identification code is

loaded into the identification data register on the rising

edge of TCK following entry into the capture-DR state.

Shift-DR can be used to shift the identification code

out serially through TDO. During test-logic-reset, the

IDCODE instruction is forced into the instruction register.

The identification code always has a ‘1’ in the LSB posi-

tion. The next 11 bits identify the manufacturer’s JEDEC

number and number of continuation bytes followed by

16 bits for the device and 4 bits for the version. See

Table 29.

USERCODE: When the USERCODE instruction latches

into the parallel instruction register, the user-code data

register is selected. The device user-code loads into the

user-code data register on the rising edge of TCK fol-

lowing entry into the capture-DR state. Shift-DR can be

used to shift the user-code out serially through TDO. See

Table 30. This instruction can be used to help identify

multiple MAX16067 devices connected in a JTAG chain.

LOAD ADDRESS: This is an extension to the standard

IEEE 1149.1 instruction set to support access to the

memory in the MAX16067. When the LOAD ADDRESS

instruction latches into the instruction register, TDI con-

nects to TDO through the 8-bit memory address test

data register during the shift-DR state.

READ DATA: This is an extension to the standard

IEEE 1149.1 instruction set to support access to the

memory in the MAX16067. When the READ instruction

latches into the instruction register, TDI connects to TDO

through the 8-bit memory read test data register during

the shift-DR state.

WRITE DATA: This is an extension to the standard

IEEE 1149.1 instruction set to support access to the

memory in the MAX16067. When the WRITE instruction

latches into the instruction register, TDI connects to TDO

through the 8-bit memory write test data register during

the shift-DR state.

REBOOT: This is an extension to the standard IEEE

1149.1 instruction set to initiate a software controlled

reset to the MAX16067. When the REBOOT instruc-

tion latches into the instruction register, the MAX16067

resets and immediately begins the boot-up sequence.

SAVE: This is an extension to the standard IEEE 1149.1

instruction set that triggers a fault log. The current ADC

conversion results along with fault information are saved

to flash depending on the configuration of the Critical

Fault Log Control register (r6Dh).

MSB

LSB

VERSION (4 BITS)

PART NUMBER (16 BITS)

MANUFACTURER (11 BITS)

FIXED VALUE (1 BIT)

0001

1000000000000001

00011001011

1

MSB

LSB

DON’T CARE

SMBUS SLAVE ID

USER ID (r8A[7:0])

00000000000000000

See Table 26

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