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MAX16067 Datasheet(PDF) 37 Page - Maxim Integrated Products |
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MAX16067 Datasheet(HTML) 37 Page - Maxim Integrated Products |
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37 / 47 page  ______________________________________________________________________________________ 37 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers SMBALERT (ALERT) The MAX16067 supports the SMBus alert protocol. To enable the SMBus alert output, set r40h[4] to ‘1’, then configure GPIO1 to act as the SMBus alert (ALERT) according to Table 11. This output is open drain and uses the wired-OR configuration with other devices on the SMBus. During a fault, the MAX16067 asserts ALERT low, signaling the master that an interrupt has occurred. The master responds by sending the ARA (Alert Response Address) protocol on the SMBus. This protocol is a read byte with 09h as the slave address. The slave acknowledges the ARA (09h) address and sends its own SMBus address to the master. The slave then deasserts ALERT. The master can then query the slave and determine the cause of the fault. By checking r1C[7], the master can confirm that the MAX16067 trig- gered the SMBus alert. The master must send the ARA before clearing r1Ch[7]. Clear r1Ch[7] by writing a ‘1’. If GPIO1 is configured as the SMBus alert output but the SMBus alert feature is disabled (r40h[4] is set to ‘0’), GPIO1 acts as an additional fault output. JTAG Serial Interface The MAX16067 features a JTAG port that complies with a subset of the IEEE 1149.1 specification. Either the SMBus or the JTAG interface can be used to access internal memory; however, only one interface is allowed to run at a time. The MAX16067 contains extra JTAG instructions and registers not included in the JTAG specification that provide access to internal memory. The extra instructions include LOAD ADDRESS, WRITE, READ, REBOOT, and SAVE. Figure 13. JTAG Block Diagram TEST ACCESS PORT (TAP) CONTROLLER INSTRUCTION REGISTER [LENGTH = 5 BITS] BYPASS REGISTER [LENGTH = 1 BIT] IDENTIFICATION REGISTER [LENGTH = 32 BITS] USER CODE REGISTER [LENGTH = 32 BITS] MEMORY ADDRESS REGISTER [LENGTH = 8 BITS] MEMORY READ REGISTER [LENGTH = 8 BITS] MEMORY WRITE REGISTER [LENGTH = 8 BITS] 11111 00000 00011 00100 00101 00110 00111 MUX 2 TDO TDI TMS TCK 01000 REGISTERS AND EEPROM 01001 01010 01011 01100 MUX 1 00111 01000 01001 01010 01011 01100 REBOOT SAVE SETUSRFLSH RSTFLSHADD RSTUSRFLSH SETFLSHADD COMMAND DECODER RPU VDB |
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