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MAX16067 Datasheet(PDF) 15 Page - Maxim Integrated Products |
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MAX16067 Datasheet(HTML) 15 Page - Maxim Integrated Products |
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15 / 47 page  ______________________________________________________________________________________ 15 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Power-Up On power-up, when EN is high and the software enable bit is ‘1’, the MAX16067 begins sequencing with Slot 0. After the sequencing delay for Slot 0 expires, the sequencer advances to Slot 1, and all EN_OUT_s assigned to the slot assert. All MON_ inputs assigned to Slot 1 are monitored and when the voltage rises above the undervoltage (UV) fault threshold, the sequence delay counter is started. When the sequence delay expires, the MAX16067 proceeds to the next slot. When the tFAULT counter expires before all MON_ inputs assigned to the slot are above the fault UV threshold, a fault asserts. EN_OUT_ outputs are disabled and the MAX16067 returns to the fault state. Register r75h[4:1] sets the tFAULT delay. See Table 7 for details. After the voltages on all MON_ inputs assigned to the last slot exceed the UV fault threshold and the slot delay expires, the MAX16067 starts the reset timeout counter. After the reset timeout, RESET deasserts. See Table 22 for more information on setting the reset timeout. Power-Down Power-down starts when EN is pulled low or the software enable bit is set to ‘0.’ Power down EN_OUT_s simul- taneously or in reverse sequence mode by setting the reverse sequence bit (r75h[0]) appropriately. Set r75h[0] to ‘1’ to power down in reverse sequence. Reverse Sequence Mode When the MAX16067 is fully powered up and EN is pulled low or the software enable bit is set to ‘0’, the EN_OUT_s assigned to Slot 6 deassert, the MAX16067 waits for the Slot 6 sequence delay and then proceeds to the previous slot (Slot 5), and so on until the EN_OUT_s assigned to Slot 1 turn off. When simultaneous power- down is selected (r75h[0] is set to ‘0’), all EN_OUT_s turn off at the same time. Voltage Monitoring The MAX16067 features an internal 10-bit ADC that mon- itors the MON_ voltage inputs. An internal multiplexer cycles through each of the enabled inputs, taking less than 24Fs for a complete monitoring cycle. Each acquisi- tion takes approximately 4Fs. At each multiplexer stop, the 10-bit ADC converts the analog input to a digital result and stores the result in a register. ADC conversion results are stored in registers r00h–r0Bh (see Table 9). Use the SMBus or JTAG serial interface to read ADC conversion results. The MAX16067 provides six inputs, MON1–MON6, for voltage monitoring. Each input-voltage range is programmable in registers r43h–r44h (see Table 8). When MON_ configuration registers are set to ’11,’ MON_ voltages are not monitored and the multiplexer does not stop at these inputs, decreasing the total cycle time. These inputs cannot be configured to trigger fault conditions. The two programmable thresholds for each monitored voltage include an overvoltage and an undervoltage threshold. See the Faults section for more information on setting overvoltage and undervoltage thresholds. All voltage thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC conversion result are compared to these overvoltage and undervoltage thresholds. For any undervoltage or overvoltage condition to be monitored and any faults detected, the MON_ input must be assigned to a sequence order or set to monitoring mode as described in the Sequencing section. Inputs that are not enabled are not converted by the ADC; they contain the last value acquired before that channel was disabled. The ADC conversion result registers are reset to 00h at boot-up. These registers are not reset when a reboot command is executed. To temporarily disable voltage monitoring during voltage margining conditions, set r73h[2] to ‘1’ to enable margin- ing mode functionality. Faults, except for faults triggered by EXTFAULT pulled low externally, are not recorded when the device is in margining mode but the ADC continues to run and conversion results continue to be available. Set r73h[2] back to ‘0’ for normal functionality. Table 7. tFAULT Delay Settings r75h[4:1] FAULT DELAY 0000 120Fs 0001 150Fs 0010 250Fs 0011 380Fs 0100 600Fs 0101 1ms 0110 1.5ms 0111 2.5ms 1000 4ms 1001 6ms 1010 10ms 1011 15ms 1100 25ms 1101 40ms 1110 60ms 1111 100ms |
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