4

FN6975.0

November 19, 2009

Output Return Loss Limit

(Differential)

See 6

dB

6

4.1GHz to 11.1GHz

See 7

dB

7

Output Return Loss Limit

(Common Mode)

100MHz to 2.5GHz

See 9

dB

9

2.5GHz to 11.1GHz

-3

dB

8

Residual Deterministic Jitter

11.1Gbps; no channel attenuation;

de-emphasis disabled

0.1

UI

10

Random Jitter

0.7

Output Transition Time

20% to 80%

35

ps

11

Minimum De-Emphasis Level

0dB

Maximum De-Emphasis Level

4dB

De-Emphasis Resolution

0.5

dB

NOTES:

6. Maximum Reflection Coefficient given by equation SDDXX(dB)= -12 + 2*√(f ), with f in GHz. Established by characterization

and not production tested.

7. Maximum Reflection Coefficient given by equation SDDXX(dB)= -6.3 + 13Log10(f/5.5), with f in GHz. Established by

characterization and not production tested.

8. Limits established by characterization and are not production tested.

9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not

production tested.

11. Rise and fall times measured using a 2GHz clock with a 20ps edge rate and with de-emphasis disabled.

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS NOTES

Typical Performance Characteristics

Performance is measured using the test setup illustrated in Figure 2. The signal from the pattern generator is launched

into the chip evaluation board. The ISL35111 output signal is then visualized on a scope to determine signal integrity

parameters such as jitter.

FIGURE 2. DEVICE CHARACTERIZATION TEST SETUP

3A. DE-EMPHASIS 0

3B. DE-EMPHASIS 6

P a tte r n

G ene r a to r

IS L 3 5 111 E v al

Bo a r d

O s c illo s c o p e

ISL35111