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AT45DB081D Datasheet(PDF) 39 Page - ATMEL Corporation |
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AT45DB081D Datasheet(HTML) 39 Page - ATMEL Corporation |
39 / 54 page 39 3596L–DFLASH–04/09 AT45DB081D 21.6 Reset Timing Note: The CS signal should be in the high state before the RESET signal is deasserted. 21.7 Command Sequence for Read/Write Operations for Page Size 256 Bytes (Except Status Register Read, Manufacturer and Device ID Read) 21.8 Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status Register Read, Manufacturer and Device ID Read) CS SCK RESET SO (OUTPUT) HIGH IMPEDANCE HIGH IMPEDANCE SI (INPUT) tRST tREC tCSS SI (INPUT) CMD 8 bits 8 bits 8 bits Page Address (A19 - A8) X X X X X X X X X X X X X X X LSB X X X X X X X X Byte/Buffer Address (A7 - A0/BFA7 - BFA0) MSB 4 Don’t Care Bits Page Address (PA11 - PA0) Byte/Buffer Address (BA8 - BA0/BFA8 - BFA0) SI (INPUT) CMD 8 bits 8 bits 8 bits X X X X X X X X X X X X LSB X X X X X X X X MSB 3 Don’t Care Bits X X X X |
Similar Part No. - AT45DB081D_09 |
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Similar Description - AT45DB081D_09 |
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