EBD10RD4ABFA

Preliminary Data Sheet E0274E40 (Ver. 4.0)

11

DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V)

Parameter

Symbol

Grade

max.

Unit

Test condition

Notes

Operating current (ACTV-PRE)

IDD0

-6B

-7A, -7B

3165

2830

mA

CKE ≥ VIH,

tRC = tRC (min.)

1, 2, 9

Operating current

(ACTV-READ-PRE)

IDD1

-6B

-7A, -7B

3525

3190

mA

CKE ≥ VIH, BL = 4,

CL = 3.5,

tRC = tRC (min.)

1, 2, 5

Idle power down standby current

IDD2P

-6B

-7A, -7B

520

454

mA

CKE ≤ VIL

4

Floating idle standby current

IDD2F

-6B

-7A, -7B

1185

1030

mA

CKE ≥ VIH, /CS ≥ VIH,

DQ, DQS, DM = VREF

4, 5

Quiet idle standby current

IDD2Q

-6B

-7A, -7B

915

850

mA

CKE ≥ VIH, /CS ≥ VIH,

DQ, DQS, DM = VREF

4, 10

Active power down

standby current

IDD3P

-6B

-7A, -7B

825

760

mA

CKE ≤ VIL

3

Active standby current

IDD3N

-6B

-7A, -7B

1725

1480

mA

CKE ≥ VIH, /CS ≥ VIH

tRAS = tRAS (max.)

3, 5, 6

Operating current

(Burst read operation)

IDD4R

-6B

-7A, -7B

4065

3460

mA

CKE ≥ VIH, BL = 2,

CL = 3.5

1, 2, 5, 6

Operating current

(Burst write operation)

IDD4W

-6B

-7A, -7B

4065

3460

mA

CKE ≥ VIH, BL = 2,

CL = 3.5

1, 2, 5, 6

Auto refresh current

IDD5

-6B

-7A, -7B

5685

5260

mA

tRFC = tRFC (min.),

Input ≤ VIL or ≥ VIH

Self refresh current

IDD6

-6B

-7A, -7B

538

472

mA

Input ≥ VDD – 0.2 V

Input ≤ 0.2 V

Operating current

(4 banks interleaving)

IDD7A

-6B

-7A, -7B

8025

6880

mA

BL = 4

5, 6, 7

Notes. 1. These IDD data are measured under condition that DQ pins are not connected.

2. One bank operation.

3. One bank active.

4. All banks idle.

5. Command/Address transition once per one cycle.

6. Data/Data mask transition twice per one cycle.

7. 4 banks active. Only one bank is running at tRC = tRC (min.)

8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.

9. Command/Address transition once every two clock cycles.

10. Command/Address stable at ≥ VIH or ≤ VIL.

DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)

(DDR SDRAM Component Specification)

Parameter

Symbol

min.

max.

Unit

Test condition

Notes

Input leakage current

IL

–2

2

µA

VDD ≥ VIN ≥ VSS

Output leakage current

IOZ

–5

5

µA

VDDQ ≥ VOUT ≥ VSS

Output high current

IOH

–15.2

—

mA

VOUT = 1.95V

Output low current

IOL

15.2

—

mA

VOUT = 0.35V