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EDS1232ECBH-9ATT Datasheet(PDF) 25 Page - Elpida Memory |
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EDS1232ECBH-9ATT Datasheet(HTML) 25 Page - Elpida Memory |
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25 / 50 page  EDS1232ECBH-9ATT Preliminary Data Sheet E0878E10 (Ver. 1.0) 25 Operation of the SDRAM Read/Write Operations Bank active Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The /CAS latency and burst length must be specified at the mode register. READ CLK Command DQ ACT Row Column Address CL = 2 CL = 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 tRCD CL = /CAS latency Burst Length = 4 /CAS Latency READ CLK Command DQ ACT Row Column out 0 out 6 out 7 Address out 0 out 1 out 4 out 5 out 0 out 1 out 2 out 3 BL = 1 out 0 out 1 out 2 out 3 BL = 2 BL = 4 BL = 8 tRCD BL : Burst Length /CAS Latency = 2 Burst Length |
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