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EDS1232ECBH-9ATT Datasheet(PDF) 38 Page - Elpida Memory

Part # EDS1232ECBH-9ATT
Description  128M bits SDRAM 128M bits SDRAM
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDS1232ECBH-9ATT Datasheet(HTML) 38 Page - Elpida Memory

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EDS1232ECBH-9ATT
Preliminary Data Sheet E0878E10 (Ver. 1.0)
38
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
Bank 0
Active
ACT
ROW
ACT
ROW
Bank 0
Active
tRC
Bank Active to Bank Active for Same Bank
CLK
Command
Address
BS
Bank 0
Active
Bank 3
Active
ACT
ROW:0
ACT
ROW:1
tRRD
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
Command
Address
Mode
Register Set
Extended Mode
Register Set
if needed
Bank
Active
MRS
lMRD
lMRD
EMRS
OPCODE
BS & ROW
OPCODE
ACT
Mode register set to Bank active command interval


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