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EDS1232ECBH-9ATT Datasheet(PDF) 37 Page - Elpida Memory

Part # EDS1232ECBH-9ATT
Description  128M bits SDRAM 128M bits SDRAM
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDS1232ECBH-9ATT Datasheet(HTML) 37 Page - Elpida Memory

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EDS1232ECBH-9ATT
Preliminary Data Sheet E0878E10 (Ver. 1.0)
37
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK
in A0
in A1
in A2
Command
DQ
WRIT
PRE/PALL
DQM
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
in A0
in A1
in A2
Command
DQ
WRIT
PRE/PALL
in A3
DQM
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))


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