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EDS1232ECBH-9ATT Datasheet(PDF) 31 Page - Elpida Memory

Part # EDS1232ECBH-9ATT
Description  128M bits SDRAM 128M bits SDRAM
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDS1232ECBH-9ATT Datasheet(HTML) 31 Page - Elpida Memory

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EDS1232ECBH-9ATT
Preliminary Data Sheet E0878E10 (Ver. 1.0)
31
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the
same bank as the preceding write command, the second write can be performed after an interval of no less than
1 clock. In the case of burst writes, the second write command has priority.
CLK
Command
DQ
in B3
Address
in B1
in B2
BS
ACT
Row
Column A
WRIT
WRIT
Column B
in A0
in B0
Bank0
Active
Column =A
Write
Column =B
Write
Burst Write Mode
BL = 4
Bank 0
WRITE to WRITE Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two write commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. In the case of burst write, the second write
command has priority.
CLK
Command
DQ
in B3
Address
in B1
in B2
BS
ACT
Row 0
Row 1
ACT
WRIT
Column A
in A0
in B0
Bank0
Active
Bank3
Active
Bank0
Write
Bank3
Write
WRIT
Column B
Burst Write Mode
BL = 4
WRITE to WRITE Command Interval (different bank)


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