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EDS1232ECBH-9ATT Datasheet(PDF) 22 Page - Elpida Memory

Part # EDS1232ECBH-9ATT
Description  128M bits SDRAM 128M bits SDRAM
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDS1232ECBH-9ATT Datasheet(HTML) 22 Page - Elpida Memory

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EDS1232ECBH-9ATT
Preliminary Data Sheet E0878E10 (Ver. 1.0)
22
Mode Register and Extended Mode Register Configuration
Mode Register Set
The mode register is set by the input to the address pins (A0 to A11, BA0 and BA1) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A8, A9, A10, A11: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode,
and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column address
specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of
the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the /CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
A2
A1 A0
Burst length
00
0
1
00
1
2
01
0
4
01
1
8
11
1
BT=0
BT=1
10
0
R
11
0
R
1
2
4
8
R
R
R
A3
0
Sequential
1
Interleave
Burst type
A6 A5
A4
CAS latency
00
0
R
00
1
R
01
0
2
01
1
3
1X
X
R
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A9
0
Write mode*
A8
0
Burst read and burst write
1
Burst read and single write
0
10
1
R
R
F.P.: Full Page
R is Reserved (inhibit)
X: 0 or 1
A11
A10
A10
X
A11
X
00
BA0
BA1
BA1 BA0
0
0
0
0
F.P.
Note: Any other combinations of above are reserved at mode register set.
Mode Register Set


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