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EDS1232ECBH-9ATT Datasheet(PDF) 8 Page - Elpida Memory |
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EDS1232ECBH-9ATT Datasheet(HTML) 8 Page - Elpida Memory |
8 / 50 page ![]() EDS1232ECBH-9ATT Preliminary Data Sheet E0878E10 (Ver. 1.0) 8 Test Conditions • Input and output timing reference levels: VDDQ × 0.5 • Input waveform and output load: See following figures tT 1.6V 1.4V 0.3V 0.2V input tT I/O CL Output load Relationship Between Frequency and Minimum Latency Parameter -9A Frequency (MHz) 111 tCK (ns) Symbol 9 Unit Notes Active command to column command (same bank) lRCD 2 tCK 1 Active command to active command (same bank) lRC 8 tCK 1 Active command to precharge command (same bank) lRAS 6 tCK 1 Precharge command to active command (same bank) lRP 2 tCK 1 Write recovery or data-in to precharge command (same bank) lDPL 2 tCK 1 Active command to active command (different bank) lRRD 2 tCK 1 Self refresh exit time lSREX 1 tCK 2 Last data in to active command (Auto precharge, same bank) lDAL 4 tCK = [lDPL + lRP] Self refresh exit to command input lSEC 8 tCK = [lRC] 3 Precharge command to high impedance (CL = 2) lHZP 2 tCK (CL = 3) lHZP 3 tCK Last data out to active command (Auto precharge, same bank) lAPR 1 tCK Last data out to precharge (early precharge) (CL = 2) lEP –1 tCK (CL = 3) lEP –2 tCK Column command to column command lCCD 1 tCK Write command to data in latency lWCD 0 tCK DQM to data in lDID 0 tCK DQM to data out lDOD 2 tCK CKE to CLK disable lCLE 1 tCK Mode register set to active command lMRD 2 tCK /CS to command disable lCDD 0 tCK Power down exit to command input lPEC 1 tCK Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP] |
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