EDS1232ECBH-9ATT datasheet(7/50 Pages) ELPIDA

Part #	EDS1232ECBH-9ATT

Description	128M bits SDRAM 128M bits SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

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EDS1232ECBH-9ATT

Preliminary Data Sheet E0878E10 (Ver. 1.0)

7

AC Characteristics (TA = –20

°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)

-9A

Parameter

Symbol

min.

max.

Unit

Notes

System clock cycle time

(CL = 2)

tCK

9

—

ns

1

(CL = 3)

tCK

9

—

ns

1

CLK high pulse width

tCH

3

—

ns

1, 5

CLK low pulse width

tCL

3

—

ns

1, 5

Access time from CLK

tAC

—

7

ns

1, 2, 5, 6

Data-out hold time

tOH

2.5

—

ns

1, 2, 5, 6

CLK to Data-out low impedance

tLZ

0

—

ns

1, 2, 3, 5, 6

CLK to Data-out high impedance

tHZ

—

7

ns

1, 4, 6

Input setup time

tSI

2

—

ns

1, 5

Input hold time

tHI

1

—

ns

1, 5

Ref/Active to Ref/Active command period

tRC

68

—

ns

1

Active to Precharge command period

tRAS

50

120000

ns

1

Active command to column command (same bank)

tRCD

18

—

ns

1

Precharge to active command period

tRP

18

—

ns

1

Write recovery or data-in to precharge lead time

tDPL

18

—

ns

1

Last data into active latency

tDAL

2CLK + 18ns

—

Active (a) to Active (b) command period

tRRD

18

—

ns

1

Transition time (rise and fall)

tT

0.5

1.0

ns

Refresh period

(4096 refresh cycles)

tREF

—

64

ms

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 0.5

× VDDQ.

2. Access time is measured at 0.5

× VDDQ. Load condition is CL = 30pF.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

5. If tT ≥ 1ns, each parameters is changed as follows;

tAC, tOH, tLZ: should be added (tT (rise)/2 – 0.5)

tCH, tCL, tSI, tHI: should be added {(tT (rise) + tT (fall))/2 – 1}

6. Driver strength is Half condition.

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