EDS1232ECBH-9ATT datasheet(5/50 Pages) ELPIDA

Part #	EDS1232ECBH-9ATT

Description	128M bits SDRAM 128M bits SDRAM

Download	50 Pages

Scroll/Zoom	100%

Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

Logo

5 / 50 page

EDS1232ECBH-9ATT

Preliminary Data Sheet E0878E10 (Ver. 1.0)

5

DC Characteristics 1 (TA = –20

°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)

Parameter

/CAS latency

Symbol

Grade

max.

Unit

Test condition

Notes

Operating current

IDD1

60

mA

Burst length = 1

tRC = tRC (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

1, 2, 3

Standby current in power down

IDD2P

2

mA

CKE ≤ 0.3V,

tCK = tCK (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

6

Standby current in power down

(input signal stable)

IDD2PS

2

mA

CKE ≤ 0.3V, tCK =

∞

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

7

Standby current in non power down

IDD2N

15

mA

CKE, /CS = VIH,

tCK = tCK (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

4

Standby current in non power down

(input signal stable)

IDD2NS

7

mA

CKE = VIH, tCK =

∞,

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

8

Active standby current in power down

IDD3P

4

mA

CKE ≤ VIL,

tCK = tCK (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

1, 2, 6

Active standby current in power down

(input signal stable)

IDD3PS

3

mA

CKE ≤ VIL, tCK =

∞

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

2, 7

Active standby current in non power down IDD3N

20

mA

CKE, /CS = VIH,

tCK = tCK (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

1, 2, 4

Active standby current in non power down

(input signal stable)

IDD3NS

10

mA

CKE = VIH, tCK =

∞,

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

2, 8

Burst operating current

IDD4

75

mA

tCK = tCK (min.),

BL = 4

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

1, 2, 5

Refresh current

IDD5

140

mA

tRC = tRC (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

3

Self refresh current

IDD6

3

mA

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output

open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, CLK operating current.

7. After power down mode, no CLK operating current.

8. Input signals are VIH or VIL fixed.

Similar Part No. - EDS1232ECBH-9ATT

Manufacturer	Part #	Datasheet	Description
Elpida Memory	EDS1232ECBH-9A	739Kb / 50P	128M bits SDRAM
Elpida Memory	EDS1232ECBH-9A-E	739Kb / 50P	128M bits SDRAM

More results

Similar Description - EDS1232ECBH-9ATT

Manufacturer	Part #	Datasheet	Description
Elpida Memory	EDS1216AHTA	619Kb / 50P	128M bits SDRAM
	EDS1232AATA	644Kb / 53P	128M bits SDRAM
	EDS1232AABB	566Kb / 55P	128M bits SDRAM
	EDS1208AATA	723Kb / 49P	128M bits SDRAM
	EDS1232ECBH-75	739Kb / 50P	128M bits SDRAM
	EDS1232JCBH-6B	738Kb / 50P	128M bits SDRAM
	EDS1232AHTA	628Kb / 50P	128M bits SDRAM
	EDS1232ECBH-9A	739Kb / 50P	128M bits SDRAM
	EDS1232JHTA	743Kb / 50P	128M bits SDRAM
	EDS1216AATA	702Kb / 49P	128M bits SDRAM

More results

EDS1232ECBH-9ATT Datasheet(PDF) 5 Page - Elpida Memory

EDS1232ECBH-9ATT Datasheet(HTML) 5 Page - Elpida Memory

Similar Part No. - EDS1232ECBH-9ATT

Similar Description - EDS1232ECBH-9ATT

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL