EBE51RD8AEFA-6

Data Sheet E0789E11 (Ver. 1.1)

9

Differential Clock Net Wiring (CK0, /CK0)

0ns (nominal)

120

Ω

120

Ω

CK0

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl

be set to 0ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not

from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired

in a similar manner.

4. Termination resistors for the PLL feedback path clocks are located as close to the

input pin of the PLL as possible.

C

/CK0

SDRAM

Register 1

PLL

Feedback in

IN

OUT1

OUT'N'

Feedback out

120

Ω

C

120

Ω