ESMT

M12L128168A

Operation temperature condition -40

Elite Semiconductor Memory Technology Inc.

Publication Date: Oct. 2007

Revision: 1.2

14/43

Write command

( CS , CAS , WE = Low, RAS = High)

If the mode register is in the burst write mode, this command sets the burst start

address given by the column address to begin the burst write operation. The first

write data in burst can be input with this command with subsequent data on following

clocks.

Read command

( CS , CAS = Low, RAS , WE = High)

Read data is available after CAS latency requirements have been met.

This command sets the burst start address given by the column address.

CBR (auto) refresh command

( CS , RAS , CAS = Low, WE , CKE = High)

This command is a request to begin the CBR refresh operation. The refresh

address is generated internally.

Before executing CBR refresh, all banks must be precharged.

After this cycle, all banks will be in the idle (precharged) state and ready for a

row activate command.

M12L128168A cannot accept any other command.

CLK

CLK

CKE

CKE

CS

CS

RAS

RAS

WE

WE

A12, A13

(Bank select)

A12, A13

(Bank select)

A10

A10

Add

Add

CAS

CAS

H

H

Col.

Fig. 4 Column address and

write command

Fig. 5 Column address and

read command

CLK

CKE

CS

RAS

WE

A12, A13

(Bank select)

A10

Add

CAS

H

Fig. 6 Auto refresh command

Col.