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STK14D88
Document Number: 001-52037 Rev. **
Page 2 of 17
Pin Configurations
Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC
Pin Descriptions
Pin Name
I/O
Description
A14-A0
Input
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
DQ7-DQ0
I/O
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
E
Input
Chip Enable: The active low E input selects the device
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address location
latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
VCC
Power Supply
Power: 3.0V, +20%, -10%
HSB
I/O
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection Optional).
VCAP
Power Supply
AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS
Power Supply
Ground
NC
No Connect
Unlabeled pins have no internal connections.
48-Pin SSOP
TOP
VSS
A14
A12
A7
A6
DQ0
DQ1
VCC
DQ2
A3
A2
A1
VCAP
A13
A8
A9
A11
A10
DQ7
DQ6
VSS
A0
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
E
NC
NC
23
24
A5
NC
NC
NC
NC
NC
NC
A4
48
47
46
45
VCC
HSB
NC
NC
W
NC
NC
DQ5
DQ3
DQ4
G
NC
NC
32-SOIC
TOP
VSS
A14
A12
A7
A6
DQ0
VCAP
A13
A8
A9
A11
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A5
A4
32
31
30
29
VCC
HSB
W
A3
A2
A1
A0
DQ1
DQ2
A10
DQ7
DQ5
DQ3
DQ4
DQ6
NC
NC
E
G
Relative PCB Area Usage[1]
Note
1. See “Package Diagrams” on page 15 for detailed package size specifications.
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