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STK14D88
Document Number: 001-52037 Rev. **
Page 5 of 17
Figure 5. SRAM READ Cycle 2: E Controlled [4, 7]
SRAM READ Cycles #1 and #2
NO.
Symbols
Parameter
STK14D88-25 STK14D88-35 STK14D88-45
Unit
Min
Max
Min
Max
Min
Max
#1
#2
Alt.
1tELQV
tACS
Chip Enable Access Time
25
35
45
ns
2tAVAV
[4]
tELEH
[4]
tRC
Read Cycle Time
25
35
45
ns
3tAVQV
[5]
tAVQV
[5]
tAA
Address Access Time
25
35
45
ns
4tGLQV
tOE
Output Enable to Data Valid
12
15
20
ns
5tAXQX
[5]
tAXQX
[5]
tOH
Output Hold after Address Change
3
3
3
ns
6tELQX
tLZ
Address Change or Chip Enable to
Output Active
33
3
ns
7tEHQZ
[6]
tHZ
Address Change or Chip Disable to
Output Inactive
10
13
15
ns
8tGLQX
tOLZ
Output Enable to Output Active
0
0
0
ns
9tGHQZ
[6]
tOHZ
Output Disable to Output Inactive
10
13
15
ns
10
tELICCH
[3]
tPA
Chip Enable to Power Active
0
0
0
ns
11
tEHICCL
[3]
tPS
Chip Disable to Power Standby
25
35
45
ns
Figure 4. SRAM READ Cycle 1: Address Controlled [4, 5, 6]
Notes
4. W must be high during SRAM READ cycles.
5. Device is continuously selected with E and G both low.
6. Measured ± 200mV from steady state output voltage.
7. HSB must remain high during READ and WRITE cycles.
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
2
29
11
7
9
10
8
4
3
6
1
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