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CDCE62002 Datasheet(PDF) 31 Page - Texas Instruments |
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CDCE62002 Datasheet(HTML) 31 Page - Texas Instruments |
31 / 49 page OUTPUT BLOCK ClockDividerModule 1 UxP UxN SYNTH Sync Pulse Enable LVDS ClockDividerModule 0 LVPECL OutputBufferControl Registers 0 18 17 16 15 Registers 0 22 21 20 19 OUTPUT 0 OUTPUT 1 CDCE62002 www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009 The output block includes two identical output channels. Each output channel comprises of a clock divider module, and a universal output buffer as shown in Figure 26. Figure 26. CDCE62002 Output Channel Table 13. CDCE62002 Output Divider Settings OUTPUT DIVIDERS SETTING DIVIDER 0 → 0.18 0.17 0.16 0.15 DIVIDE RATIO DIVIDER 1 → 0.22 0.21 0.20 0.19 0 0 0 0 Disabled 0 0 0 1 /1 0 0 1 0 /2 0 0 1 1 /3 0 1 0 0 /4 0 1 0 1 /5 0 1 1 0 /6 0 1 1 1 Disabled 1 0 0 0 /8 1 0 0 1 Disabled 1 0 1 0 /10 1 0 1 1 /20 1 1 0 0 /12 1 1 0 1 /24 1 1 1 0 /16 1 1 1 1 /32 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Link(s): CDCE62002 |
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