CDCE62002 datasheet(3/49 Pages) TI

Part #	CDCE62002

Description	Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

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Manufacturer	TI [Texas Instruments]

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DEVICE INFORMATION

PIN FUNCTIONS

CDCE62002

www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009

Table 1. CDCE62002 Pin Functions(1)

TYPE

DESCRIPTION

NAME

QFN

VCC_OUT0

9,12 13,16

Power

3.3V Supply for the Output Buffers.

VCC_OUT1

There is no internal connection between VCC and AVCC. It is recommended, that each VCC

uses its own supply filter.

VCC_PLLDIV

22

Power

3.3V Supply Power for the PLL circuitry.

VCC_PLLD

4

Power

3.3V Supply Power for the PLL circuitry.

VCC_PLLA

28

A. Power

3.3V Supply Power for the PLL circuitry.

VCC_VCO

24

A. Power

3.3V Supply Power for the VCO Circuitry.

VCC_IN

31

Power

3.3V Supply Power for Input Buffer Circuitry

VCC_AUX

1

A. Power

3.3V Supply Power for Crystal/Auxiliary Input Buffer Circuitry

GND_PLLDIV

21

Ground

Ground for PLL Divider circuitry. (short to GND)

GND

PAD

Ground

Ground is on Thermal PAD. See Layout recommendation

SPI_MISO

7

OD

3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial Data

Output to the SPI bus interface.

SPI_LE

18

I

LVCMOS input, control Latch Enable for Serial Programmable Interface.

Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly on the

Rising edge of PD. The input has an internal 150-k

Ω pull-up resistor

SPI_CLK

17

I

LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis.

SPI_MOSI

8

I

LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62002 for the

SPI bus interface.

PD

6

I

PD or Power Down Pin is an active low pin and can be activated externally or via the

corresponding Bit in SPI Register 2

In case of PD is asserted , the Device shuts Down and after PD goes high the EEPROM

Loads into RAM and the VCO core re-starts calibration, PLL will try to relock and the

Output dividers will get re-initiated. The LVPECL outputs are static low and high

respectively and the LVCMOS outputs are all low or high if inverted. The input has an

internal 150-k

Ω pull-up resistor if left unconnected it will default to logic level “1”.

Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly into

RAM on the Rising edge of PD.

AUX_IN

2

I

Auxiliary Input is a Crystal input pin that connect to an internal oscillator circuitry. This

input can also be driven by an LVCMOS signal.

This input also serves as the External Feedback Input that feeds directly to the PFD.

REF+

29

I

Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Reference Clock.

REF–

30

I

Universal Input Buffer (LVPECL, LVDS,) negative input for the Reference Clock. In case of

LVCMOS signaling pull-down this pin.

PLL_LOCK

32

O

PLL Lock indicator

TESTSYNC

19

I

Test Point for Use for TI Internal SYNC Testing.

REG_CAP1

5

Analog

Capacitor for the internal Regulator. Connect to a 10

µF Capacitor (Y5V)

REG_CAP2

27

Analog

Capacitor for the internal Regulator. Connect to a 10

µF Capacitor (Y5V)

REG_CAP3

20

Analog

Capacitor for the internal Regulator. Connect to a 10

µF Capacitor (Y5V)

REG_CAP4

23

Analog

Capacitor for the internal Regulator. Connect to a 10

µF Capacitor (Y5V)

VBB

3

Analog

Capacitor for the internal termination Voltage. Connect to a 1

µF Capacitor (Y5V)

EXT_LFP

25

Analog

External Loop Filter Input Positive

EXT_LFN

26

Analog

External Loop Filter Input Negative.

U0P:U0N

11,10 15,14

O

The Main outputs of CDCE62002 are user definable and can be any combination of up to

2 LVPECL outputs, 2 LVDS outputs or up to 4 LVCMOS outputs. The outputs are

U1P:U1N

selectable via SPI interface. The power-up setting is EEPROM configurable.

(1)

NOTE: All VCC pins need to be connected for the device to operate properly.

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