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CDCE62002 Datasheet(PDF) 26 Page - Texas Instruments |
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CDCE62002 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 49 page  Device Control Device OFF Active Mode Power ON Reset Power Down Sync VCO CAL Power Applied Delay Finished Power Down = ON Sync = ON Sync = OFF PLLRESET= ON External Control Pins CDCE62002 SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com Figure 19 provides a conceptual explanation of the CDCE62002 Device operation. Table 11 defines how the device behaves in each of the operational states. Figure 19. CDCE62002 Device State Control Diagram Table 11. CDCE62002 Device State Definitions Output Output SPI Port PLL State Device Behavior Entered Via Exited Via Divider Buffer Status Status Status Status Power-On After device power supply reaches Power applied to the device or Power On Reset and EEPROM OFF Disabled Disabled OFF Reset approximately 2.35V, the contents of upon exit from Power Down State loading delays are finished OR the EEPROM are copied into the Device via the PD pin set HIGH. PD pin is set LOW. Registers, thereby initializing the device hardware . VCO CAL The voltage controlled oscillator is Delay process in the Power-On Calibration Process in completed ON Enabled Disabled OFF calibrated based on the PLL settings Reset State is finished or and the incoming reference clock. After PLLRESET=ON the VCO has been calibrated, the device enters Active Mode automatically. Active Mode Normal Operation CAL Done (VCO calibration Power Down or PLLRESET=ON ON Enabled Disabled Disabled or process finished) or Sync = OFF or Enabled (from Sync State). Enabled Power Down Used to shut down all hardware and PD pin is pulled LOW. PD pin is pulled HIGH. ON Disabled Disabled Disabled Resets the device after exiting the Power Down State. Therefore, the EEPROM contents will eventually be copied into RAM after the Power Down State is exited. Sync Sync synchronizes both outputs dividers Sync Bit in device register 2 bit 8 Sync bit in device register 2 bit 8 is ON Enabled Disabled Disabled so that they begin counting at the same is set LOW set HIGH time Power Down (PD) When pulled LOW, PD activates the Power Down state which shuts down all hardware and resets the device. Restoring PD high will cause the CDCE62002 to exit the Power Down State. This causes the device to behave as if it has been powered up including copying the EEPROM contents into RAM. PD pin also has a shadowed PD bit residing in Register 2 Bit 7. When asserted Low it puts the device in Power Down Mode, but it does not load the EEPROM when the bits is disserted. NOTE: 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE62002 |
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