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CDCE62002 Datasheet(PDF) 22 Page - Texas Instruments |
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CDCE62002 Datasheet(HTML) 22 Page - Texas Instruments |
22 / 49 page Device Registers: Register 0 CDCE62002 SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com Table 7. CDCE62002 Register 0 Bit Definitions SPI RAM BIT RELATED DESCRIPTION / FUNCTION BIT BIT NAME BLOCK 0 A0 Address 0 0 1 A1 Address 1 0 2 A2 Address 2 0 3 A3 Address 3 0 4 0 INBUFSELX INBUFSELX Input Buffer Select (LVPECL,LVDS or LVCMOS) EEPROM XY(00 ) Disabled, (01) LVPECL, (10) LVDS, (11) LVCMOS 5 1 INBUFSELY INBUFSELY EEPROM The VBB internal Biasing will be determined from this setting 6 2 REFSEL Smart MUX See specific section for more detailed description and configuration EEPROM Bits(2,3) setup. 7 3 AUXSEL EEPROM 00 – RESERVED 10 – REF_IN Select 01– AUX_IN Select 11 – Auto Select ( Reference then AUX) 8 4 ACDCSEL Input Buffers If Set to “1” DC Termination, If set to “0” AC Termination EEPROM 9 5 TERMSEL Input Buffers If Set to “0” Input Buffer Internal Termination Enabled EEPROM 10 6 REFDIVIDE 0 EEPROM Reference Divider Settings. 11 7 REFDIVIDE 1 EEPROM See specific section for more detailed description and configuration 12 8 REFDIVIDE 2 EEPROM setup. 13 9 REFDIVIDE 3 EEPROM 14 10 EXTFEEDBACK External Feedback to PFD from AUX Input enabled when set to “1” EEPROM 15 11 I70TEST TEST Set to “0” for Normal Operation. EEPROM 16 12 ATETEST TEST Set to “0” for Normal Operation. EEPROM 17 13 LOCKW(0) PLL Lock Lock-detect window Bit 0 EEPROM 18 14 LOCKW(1) PLL Lock Lock-detect window Bit 1 EEPROM 19 15 OUT0DIVRSEL0 Output 0 Output 0 Divider Settings. EEPROM See specific section for more detailed description and configuration 20 16 OUT0DIVRSEL1 Output 0 EEPROM setup. 21 17 OUT0DIVRSEL2 Output 0 EEPROM 22 18 OUT0DIVRSEL3 Output 0 EEPROM 23 19 OUT1DIVRSEL0 Output 1 Output 1 Divider Settings. EEPROM See specific section for more detailed description and configuration 24 20 OUT1DIVRSEL1 Output 1 EEPROM setup. 25 21 OUT1DIVRSEL2 Output 1 EEPROM 26 22 OUT1DIVRSEL3 Output 1 EEPROM 27 23 HIPERORMANCE Output 0 & 1 High Performance, If this Bit is set to “1”: EEPROM – Increase the Bias in the device to achieve Best Phase Noise on the Output Divider – It changes the LVPECL Buffer to Hi Swing in LVPECL. – It increases the current consumption by 20mA (Typical) 28 24 OUTBUFSEL0X Output 0 Output Buffer mode select for OUTPUT “0 ”. EEPROM (X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL 29 25 OUTBUFSEL0Y Output 0 EEPROM 30 26 OUTBUFSEL1X Output 1 Output Buffer mode select for OUTPUT “1 ”. EEPROM (X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL 31 27 OUTBUFSEL1Y Output 1 EEPROM 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE62002 |
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