SPI (Serial Peripheral Interface)

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Address

Bits

(4)

Lastin /

Lastout

FirstIn /

FirstOut

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPIMaster (Host)

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPISlave (CDCE62002)

DeviceRegisterN

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SPIRegister

DataBits (28)

CDCE62002

The serial interface of CDCE62002 is a simple bidirectional SPI interface for writing and reading to and from the

device registers. It implements a low speed serial communications link in a master/slave topology in which the

CDCE62002 is a slave. The SPI consists of four signals:

•

SPI_CLK: Serial Clock (Output from Master) – the CDCE62002 clocks data in and out on the rising edge of SPI_CLK. Data transitions

therefore occur on the falling edge of the clock.

•

SPI_MOSI: Master Output Slave Input (Output from Master).

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SPI_MISO: Master Input Slave Output (Output from Slave)

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SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high, no data transfer can take

place.

The CDCE62002 implements data fields that are 28-bits wide. In addition, it contains 3 registers, each

comprising a 28 bit data field. Therefore, accessing the CDCE62002 requires that the host program append a

4-bit address field to the front of the data field as follows:

Figure 16. CDCE62002 SPI Communications Format

Copyright © 2009, Texas Instruments Incorporated

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Product Folder Link(s): CDCE62002