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CDCE62002 Datasheet(PDF) 7 Page - Texas Instruments |
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CDCE62002 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 49 page COMPUTING THE OUTPUT FREQUENCY Output Divider 0 U0P U0N Output Divider 1 U1P U1N PFD/ CP Prescaler Feedback Divider Input Divider Reference Divider EXT_LFP EXT_LFN F R I P O F OUT Fin OUT IN F F F R I O = × × × (1) OUT 1.750GHz O P F 2.356GHz < × × < (2) IN COMP F F R I = × (3) CDCE62002 www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009 Figure 7 presents the block diagram of the CDCE62002 synthesizer highlighting the clock path for a single output. It also identifies the following regions containing dividers comprising the complete clock path: • R: Is the Reference divider values. • O: The output divider value (see Output Block for more details) • I: The input divider value (see Synthesizer Block for more details) • P: The Prescaler divider value (see Synthesizer Block of more details) • F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for more details) Figure 7. CDCE62002 Clock Path – Synthesizer With respect to Figure 7, any output frequency generated by the CDCE62002 relates to the input frequency connected to the Synthesizer Block by the following equation: Equation 1 holds true subject to the following constraints: And the comparison frequency FCOMP, 40.0 kHz ≤ FCOMP ≤ 40 MHz Where: Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): CDCE62002 |
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