CDCE62002 datasheet(5/49 Pages) TI

Part #	CDCE62002

Description	Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

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Manufacturer	TI [Texas Instruments]

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Interface and Control Block

Device

Hardware

StaticRAM DeviceRegisters

Register 0

Register 1

Register 2

Interface

&

Control

PD

SPI_ LE

SPI_ CLK

SPI_ MOSI

SPI_ MISO

EEPROM

DeviceRegisters

Register 0

Register 1

Register 2

Input Block

REF_IN

XTAL/

AUX_IN

LVPECL /LVDS 500 MHz

LVCMOS 250 MHz

Crystal : 2 MHz – 42 MHz

SingleEnded : 2 MHz - 75 MHz

Synthesizer

Reference

SmartMUX

Control

ReferenceDivider

/1 - /8

CDCE62002

www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009

The CDCE62002 is a highly flexible and configurable architecture and as such contains a number of registers so

that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM

determine device configuration at all times. On power-up, the CDCE62002 copies the contents of the EEPROM

into the RAM and the device begins operation based on the default configuration stored in the EEPROM.

Systems that do not have a host system to communicate with the CDCE62002 use this method for device

configuration. The CDCE62002 provides the ability to lock the EEPROM; enabling the designer to implement a

fault tolerant design. After power-up, the host system may overwrite the contents of the RAM via the SPI (Serial

Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62002 during system

operation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM, if the EEPROM is

unlocked.

Figure 3. CDCE62002 Interface and Control Block

The Input Block includes one Universal Input Buffer and an Auxiliary Input. The Input Block buffers the incoming

signals and facilitates signal routing to the Internal Synthesizer Block via the smart multiplexer (called the Smart

MUX). The CDCE62002 can divide the REF_IN signal via the dividers present on the inputs of the first stage of

the Smart MUX.

Figure 4. CDCE62002 Input Block

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