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CDCE62002 Datasheet(PDF) 39 Page - Texas Instruments |
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CDCE62002 Datasheet(HTML) 39 Page - Texas Instruments |
39 / 49 page ![]() APPLICATION INFORMATION AND GENERAL USAGE HINTS Clock Generator XTAL / AUX _IN Output Divider 0 U0P U0N PFD/ CP Prescaler Feedback Divider Input Divider Smart MUX Output Divider 1 U1P U1N External Feedback Option Output Divider 0 U0P U0N Output Divider 1 U1P U1N PFD/ CP Prescaler Feedback Divider Divby 1 Divby 1 REF_IN FB LF 100nF CDCE62002 www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009 The CDCE62002 can generate 1 to 4 low noise clocks from a single crystal or crystal oscillator as follows: Figure 32. CDCE62002 as a Clock Generator The CDCE62002 has a limited optional external feedback path that give access to the PFD inside the device. This option enables customers to implement complex or custom PLL designed to control the VCO inside the CDCE62002. In addition, the External feedback allows the device to operate in a deterministic delay mode where the reference to output delay is fixed but dependable on the routing path length from the outputs to the auxiliary input pin. Figure 33 illustrates how the output is loopback to the Auxiliary Input in bypass mode to put the device in fixed delay mode. Figure 33. CDCE62002 External Feedback Example This function is limited by the output divider divide ratio and can be implemented when one of the outputs is set from 10.94 MHz to 40.00MHz. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link(s): CDCE62002 |
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