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CDCE62002 Datasheet(PDF) 32 Page - Texas Instruments |
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CDCE62002 Datasheet(HTML) 32 Page - Texas Instruments |
32 / 49 page SYNTHESIZER BLOCK PFD/ CP Prescaler /2,/3,/4,/5 InputDivider /1 - /256 SMART _MUX SYNTH 70 kHz – 400 kHz /1,/2,/5,/8,/10,/16,/20 /8 - /1280 FeedbackDivider 1.75 GHz – 2.356 GHz Register 1 22 23 24 25 LoopFilterandChargePump CurrentSettings 1 Register 1 2 3 4 5 6 7 8 InputDividerSettings Register 1 8 9 Prescaler 11 Register 1 12 13 14 15 16 17 18 FeedbackDivider Register 1 19 20 21 FeedbackBypassDivider Register 1 0 VCOSelect Input Divider CDCE62002 SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com Figure 27 provides an overview of the CDCE62002 synthesizer block. The Synthesizer Block provides a Phase Locked Loop, a partially integrated programmable loop filter, and two Voltage Controlled Oscillators (VCO). The synthesizer block generates an output clock called “SYNTH” and drives it onto the Internal Clock Distribution Bus. Figure 27. CDCE62002 Synthesizer Block The Input Divider divides the clock signal selected by the Smart Multiplexer and presents the divided signal to the Phase Frequency Detector / Charge Pump of the frequency synthesizer. Table 14. CDCE62002 Input Divider Settings INPUT DIVIDER SETTINGS DIVIDE SELINDIV7 SELINDIV6 SELINDIV5 SELINDIV4 SELINDIV3 SELINDIV2 SELINDIV1 SELINDIV0 RATIO 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 1 1 4 0 1 0 0 0 1 0 0 5 0 1 0 0 0 1 0 1 6 – – – – – – – – – – – – – – – – – – 1 1 1 1 1 1 1 1 256 32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE62002 |
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