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SN74ALS280DRE4 Datasheet(PDF) 6 Page - Texas Instruments |
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SN74ALS280DRE4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 12 page SN74ALS280, SN74AS280 9-BIT PARITY GENERATORS/CHECKERS SDAS038C – DECEMBER 1982 – REVISED DECEMBER 1994 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/ 74ALS AND 54AS/ 74AS DEVICES tPHZ tPLZ tPHL tPLH 0.3 V tPZL tPZH tPLH tPHL LOAD CIRCUIT FOR 3-STATE OUTPUTS From Output Under Test Test Point R1 S1 CL (see Note A) 7 V 1.3 V 1.3 V 1.3 V 3.5 V 3.5 V 0.3 V 0.3 V th tsu VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Timing Input Data Input 1.3 V 1.3 V 3.5 V 3.5 V 0.3 V 0.3 V High-Level Pulse Low-Level Pulse tw VOLTAGE WAVEFORMS PULSE DURATIONS Input Out-of-Phase Output (see Note C) 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 3.5 V 3.5 V 0.3 V 0.3 V VOL VOH VOH VOL Output Control (low-level enabling) Waveform 1 S1 Closed (see Note B) Waveform 2 S1 Open (see Note B) [0 V VOH VOL [3.5 V In-Phase Output 0.3 V 1.3 V 1.3 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS R2 VCC RL Test Point From Output Under Test CL (see Note A) LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS From Output Under Test Test Point CL (see Note A) RL RL = R1 = R2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms |
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