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SN74ACT7804 Datasheet(PDF) 7 Page - Texas Instruments |
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SN74ACT7804 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 11 page SN74ACT7804 512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS204C – APRIL 1992 – REVISED APRIL 1998 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating conditions (see Figures 1 through 3) ’ACT7804-20 ’ACT7804-25 ’ACT7804-40 UNIT MIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 50 40 25 MHz LDCK high or low 7 8 12 t Pulse duration UNCK high or low 7 8 12 ns tw Pulse duration PEN low 7 8 12 ns RESET low 10 10 12 D0–D17 before LDCK ↑ 5 5 5 tsu Setup time PEN before LDCK ↑ 5 5 5 ns LDCK inactive before RESET high 5 6 6 D0–D17 after LDCK ↑ 0 0 0 th Hold time LDCK inactive after RESET high 5 6 6 ns th Hold time PEN low after LDCK ↑ 3 3 3 ns PEN high after LDCK ↓ 0 0 0 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 3) PARAMETER FROM TO ’ACT7804-20 ’ACT7804-25 ’ACT7804-40 UNIT PARAMETER (INPUT) (OUTPUT) MIN TYP† MAX MIN MAX MIN MAX UNIT fmax LDCK or UNCK 50 40 25 MHz t d LDCK ↑ Any Q 9 20 9 22 9 24 ns tpd UNCK ↑ Any Q 6 11.5 15 6 18 6 20 ns tpd‡ UNCK ↑ Any Q 10.5 ns tPLH LDCK ↑ EMPTY 6 15 6 17 6 19 ns UNCK ↑ EMPTY 6 15 6 17 6 19 tPHL RESET low EMPTY 4 16 4 18 4 20 ns PHL LDCK ↑ FULL 6 15 6 17 6 19 tPLH UNCK ↑ FULL 6 15 6 17 6 19 ns tPLH RESET low FULL 4 18 4 20 4 22 ns t d LDCK ↑ AF/AE 7 18 7 20 7 22 ns tpd UNCK ↑ AF/AE 7 18 7 20 7 22 ns tPLH RESET low AF/AE 2 10 2 12 2 14 ns tPLH LDCK ↑ HF 5 18 5 20 5 22 ns tPHL UNCK ↑ HF 7 18 7 20 7 22 ns tPHL RESET low HF 3 12 3 14 3 16 ns ten OE Any Q 2 9 2 10 2 11 ns tdis OE Any Q 2 10 2 11 2 12 ns † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter is measured at CL = 30 pF (see Figure 4). operating characteristics, VCC = 5 V, TA = 25°CFigure 2 PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, f = 5 MHz 53 pF |
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