SN54HC161, SN74HC161

4BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003

13

POST OFFICE BOX 655303

APPLICATION INFORMATION

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

SN54HC161

SN74HC161

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

3.6

2.5

2.9

fclock

Clock frequency

4.5 V

18

12

14

MHz

fclock

Clock frequency

6 V

21

14

17

MHz

2 V

140

200

170

tw

Pulse duration, CLK high or low

4.5 V

28

40

36

ns

tw

Pulse duration, CLK high or low

6 V

24

36

30

ns

(unless otherwise noted) (see Note 4)

PARAMETER

FROM

TO

VCC

TA = 25°C

SN54HC161

SN74HC161

UNIT

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

3.6

2.5

2.9

fmax

4.5 V

18

12

14

MHz

fmax

6 V

21

14

17

MHz

NOTE 4: These limits apply only to applications that use more than two ’HC161 devices cascaded together.

If the ’HC161 devices are used as a single unit, or only two cascaded together, then the maximum clock

frequency that the device can use is not limited because of the glitch. In these situations, the device can be

operated at the maximum specifications.

A glitch can appear on RCO of a single ’HC161 device, depending on the relationship of ENT to CLK. Any

application that uses RCO to drive any input except an ENT of another cascaded ’HC161 device must take this

into consideration.