SN5400, SN54LS00, SN54S00

SN7400, SN74LS00, SN74S00

QUADRUPLE 2INPUT POSITIVENAND GATES

SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

1

POST OFFICE BOX 655303

Small-Outline (D, NS, PS), Shrink

Small-Outline (DB), and Ceramic Flat (W)

Packages, Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J) DIPs

Positive-NAND Gate in Small-Outline (PS)

Package

SN5400 ...J PACKAGE

SN54LS00, SN54S00 ...J OR W PACKAGE

SN7400, SN74S00 . . . D, N, OR NS PACKAGE

SN74LS00 . . . D, DB, N, OR NS PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

SN5400 ...W PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2Y

2A

2B

4Y

4B

4A

GND

3B

3A

3Y

SN74LS00, SN74S00 ...PS PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

2B

2A

2Y

1A

1B

1Y

GND

32 1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3B

1Y

NC

2A

NC

2B

SN54LS00, SN54S00 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

description/ordering information

These devices contain four independent 2-input NAND gates. The devices perform the Boolean function

Y = A

• B or Y = A + B in positive logic.

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MILPRF38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.