CDC351

1-LINE TO 10-LINE CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995

1

POST OFFICE BOX 655303

Clock-Distribution and Clock-Generation

Applications

(5-V Input and Output Voltages With 3.3-V

Switching Noise

Significantly Reduces Power Dissipation

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages

description

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with

minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure

that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended

for customer use and should be connected to GND.

The CDC351 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

A

OE

Yn

L

H

Z

H

HZ

L

LL

H

L

H

Copyright

© 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC-

ΙΙΒ is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

GND

Y10

Y9

OE

A

P0

P1

Y8

Y7

GND

GND

Y1

Y2

GND

Y3

Y4

GND

Y5

Y6

GND

DB OR DW PACKAGE

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