CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299 – APRIL 2000

3

POST OFFICE BOX 655303

logic diagram (positive logic)

1

9

10

7

3

15

14

CLR

LOAD

ENT

ENP

CLK

A

RCO

QA

† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown

on the logic diagram of the D/T flip-flops.

M1

G2

G4

3D

4R

1, 2T/1C3

4

13

B

QB

M1

G2

G4

3D

4R

1, 2T/1C3

5

12

C

QC

M1

G2

G4

3D

4R

1, 2T/1C3

6

11

D

QD

M1

G2

G4

3D

4R

1, 2T/1C3

2

LD†

CK†

CK

R

LD