CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299 – APRIL 2000

8

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

CD54AC163

CD74AC163

UNIT

VCC

MIN

MAX

MIN

MAX

UNIT

1.5 V

7

8

fclock

Clock frequency

3.3 V

± 0.3 V

64

73

MHz

5 V

± 0.5 V

90

103

1.5 V

69

61

tw

Pulse duration

CLK high or low

3.3 V

± 0.3 V

7.7

6.8

ns

5 V

± 0.5 V

5.5

4.8

↑

1.5 V

63

55

↑

A, B, C, or D

3.3 V

± 0.3 V

7

6.1

↑

5 V

± 0.5 V

5

4.4

↑

1.5 V

63

55

↑

ENP or ENT

3.3 V

± 0.3 V

9.6

8.2

t

Setup time before CLK

↑

5 V

± 0.5 V

5

4.4

ns

tsu

Setup time, before CLK

↑

1.5 V

75

66

ns

LOAD low

3.3 V

± 0.3 V

8.4

7.4

5 V

± 0.5 V

6

5.3

1.5 V

75

66

CLR inactive

3.3 V

± 0.3 V

8.4

7.4

5 V

± 0.5 V

6

5.3

↑

1.5 V

0

0

↑

A, B, C, or D

3.3 V

± 0.3 V

0

0

↑

5 V

± 0.5 V

0

0

↑

1.5 V

0

0

↑

ENP or ENT

3.3 V

± 0.3 V

0

0

th

Hold time after CLK

↑

5 V

± 0.5 V

0

0

ns

th

Hold time, after CLK

↑

1.5 V

0

0

ns

LOAD low

3.3 V

± 0.3 V

0

0

5 V

± 0.5 V

0

0

1.5 V

0

0

CLR inactive

3.3 V

± 0.3 V

0

0

5 V

± 0.5 V

0

0