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PE42552MLIB Datasheet(PDF) 6 Page - Peregrine Semiconductor Corp. |
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PE42552MLIB Datasheet(HTML) 6 Page - Peregrine Semiconductor Corp. |
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6 / 9 page  Product Specification PE42552 Page 6 of 9 ©2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions Through Line L1 WAS INDUCTOR 1 J5 142-0761-881/891 2 J1 142-0761-881/891 1 J3 142-0761-881/891 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 J4 HEADER 14 1 J2 142-0761-881/891 C1 22pF R1 DNI C2 22pF R2 DNI C3 22pF 1 J6 142-0761-881/891 R3 DNI C4 68pF 9 GND 10 GND 11 RF2 12 GND 1 GND 3 GND 2 RF1 4 GND U1 QFN50P3X3-16P R4 0 OHM L1 0 OHM LS RF2 CTRL VDD VSS RF1 Evaluation Kit The SPDT switch EK Board was designed to ease customer evaluation of Peregrine’s PE42552. The RF common port is connected through a 50 Ω transmission line via the top SMA connector, J1. RF1, RF2, RF3 and RF4 are connected through 50 Ω transmission lines via SMA connectors J3, J5, J2 and J4, respectively. A through 50 Ω transmission is available via SMA connectors J6 and J7. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The evaluation kit board is constructed of four metal layers. The dual clad top RF layer is Rogers RO4003 material with an 8 mil RF core and er = 3.55. The other two dielectric layers are FR4 for DC control and overall board strength with an cumulative board thickness of 60 mils. The RF transmission lines were designed using a Grounded co-planar waveguide with a linewidth of 15 mils and gap of 10 mils. Figure 16. Evaluation Board Layouts Figure 17. Evaluation Board Schematic Peregrine Specification 102/0404 Peregrine Specification 101/0334 |
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