Timing

Since the ATM Forum specification fully defines the line side of the UTOPIA Level 3 interface, timing for that is not replicated here. Instead, only user (FIFO) interface

timing information is presented here. The figure below shows the functional timing for FIFO reads and writes.

Figure 3: FIFO Timing

D2

D1

D0

A0

A2

A1

RD_CLK

RD_ADDR

RD_ENB

RD_DATA

D0

D1

D53

D52

...

A0

A53

A52

...

A1

WR_CLK

WR_ADDR

WR_ENB

WR_DATA