top_master.vhd

top_ing_master.vhd

top_egr_master.vhd

egr_utopia_master.vhd

ing_utopia_master.vhd

txclk

tx_data

txenb_n

txclav

tx_addr

rd_enb

rd_data

rd_flag

txprty

tx_soc

rxclk

rxdata

rxenb_n

rx_clav

rx_soc

rx_prty

rx_addr

wr_enb

wr_data

wr_flag

increment

wr_enb

wr_data

wr_flag

wr_clk

rd_enb

rd_data

rd_flag

reset_n

fifo_16.vhd/fifo_8.vhd

fifo_16.vhd/fifo_8.vhd

rd_clk

AvnetCore: Datasheet

UTOPIA Level 3 Link

Intended Use:

— Cell Processors

— Switch Fabrics

— Networking

— Telecommunications

Features:

— Function compatible with ATM Forum

— Asynchronous/synchronous FIFO using RAM

— Up to 256 phys supported

— 8/16/32 bit interfaces supported

— Simple system side FIFO interface

— Flow control and polling integrated

Targeted Devices:

— Axcelerator Family

Core Deliverables:

— Netlist Version

> Netlist compatible with the Actel Designer place and route tool

> Compiled RTL simulation model, compliant with the Actel

— RTL Version

> VHDL Source Code

— All

> User Guide

> Test Bench

Synthesis and Simulation Support:

— Other tools supported upon request

Verification:

— Test Bench

— Test Vectors

UTOPIA (Universal Test and Operations PHY Interface for ATM) level 3 defines the

interface between the ATM or LINK layer and a Physical Layer (PHY) device. The

UTOPIA level 3 standard defines a full duplex interface with a Master/Slave format. The

Slave or LINK layer device responds to the requests from the PHY or Master device.

The Master performs PHY arbitration and initiates data transfers to and from the Slave.

The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in width, at up to

104 MHz, supporting an OC48 channel at 2.5 Gbps.

Version 1.0, July 2006

Block Diagram