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UAA145 Datasheet(PDF) 4 Page - TEMIC Semiconductors |
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UAA145 Datasheet(HTML) 4 Page - TEMIC Semiconductors |
4 / 11 page ![]() UAA145 TELEFUNKEN Semiconductors Rev. A1, 29-May-96 4 (11) vsync v10,14 t t v14 v10 95 11299 ö ö ö ö h v a Figure 4. Pulse phasing P7 20mA/div. –0mA P7 2V/div. –0V 95 10105 Figure 5. Charging time 10 ms/div. Pulse Phasing Limits The pulse phasing front limit is determined by limiting the maximum shift voltage applied to Pin 8 which is thus adjustable by external circuitry. This can be done by connecting a Z-diode between Pin 8 and Pin 3. The pulse phasing rear limit, öh, is the residual phase angle of the output pulses when the shift voltage Vö is zero. Since öh coincides with the zero crossover point of the ramp, it can be adjusted by variation of the time constant CsRs (figure 14). Figure 10 shows the pulse phasing rear limit plotted as a function of Rs. Pulse Blocking The output pulses can be blocked via Pin 6, the memory content being erased whenever Pin 6 is connected to +VS (Pin 1). This effectively de-activates the pulse generator; any output pulse in the process of generation is inter- rupted. Pulse blocking can be accomplished either via relay contacts or a PNP switching transistor (figure 14). 0.1 1 10 100 0 100 200 300 400 600 RP ( kW ) 1000 95 10106 500 Sync. Time VSync.=230VX R=22k W 2 tSync. Pin16 Figure 6. Output Pulse Width The output pulse width can be varied by adjustment of Rt and Ct. In figure 11 pulse width is shown plotted as a func- tion of Rt for Ct = 50 nF. The output pulse always finishes at zero crossover. This means that if there is a minimum pulse width requirement (for example, when the load is inductive) provision must be made for a corresponding pulse phasing rear limit. The output stages are arranged so that the transistors are cut off when a pulse is produced. Consequently, the thyristor trigger pulse current flows via the external load resistors, this current being passed by the transistors during the period when no output pulse is produced. During this period the output voltage drops to the transistor saturation level and is therefore load dependent. Figure 12 shows the relationship between saturation voltage and load current. Shift Characteristic In figure 13 the angle of phase shift is shown plotted as a function of the voltage applied to Pin 8 for a pulse phasing rear limit of approximately 0 _. Because the ramp wave- form is a part of the exponential function, the shift curve is also exponential. The limitation of the shift voltage to approximately 8.5 V is due to the internal Z-diode Z4, which has a voltage spread of 7 to 9 V. The waveforms in figures 7 to 9 show the output pulse phase shift as a function of Vö. It can be seen from the oscillograms, the instants at which pulses are released coincide with the intersections of the ramp and the shift voltage. |
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