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EP2C35A15F324C6N Datasheet(PDF) 4 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 4 Page - Altera Corporation |
4 / 168 page ![]() 1–2 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2008 Features ■ DSP intellectual property (IP) cores ■ DSP Builder interface to The Mathworks Simulink and Matlab design environment ■ DSP Development Kit, Cyclone II Edition Cyclone II devices include a powerful FPGA feature set optimized for low-cost applications including a wide range of density, memory, embedded multiplier, and packaging options. Cyclone II devices support a wide range of common external memory interfaces and I/O protocols required in low-cost applications. Parameterizable IP cores from Altera and partners make using Cyclone II interfaces and protocols fast and easy. Features The Cyclone II device family offers the following features: ■ High-density architecture with 4,608 to 68,416 LEs ● M4K embedded memory blocks ● Up to 1.1 Mbits of RAM available without reducing available logic ● 4,096 memory bits per block (4,608 bits per block including 512 parity bits) ● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36 ● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes ● Byte enables for data input masking during writes ● Up to 260-MHz operation ■ Embedded multipliers ● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance ● Optional input and output registers ■ Advanced I/O support ● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL ● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL ● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces ● PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore® function |
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