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EP2C35A15F324C6N Datasheet(PDF) 38 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 38 Page - Altera Corporation |
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38 / 168 page  2–26 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 Global Clock Network & Phase-Locked Loops Table 2–4 describes the PLL features in Cyclone II devices. Table 2–4. Cyclone II PLL Features Feature Description Clock multiplication and division m / (n × post-scale counter) m and post-scale counter values (C0 to C2) range from 1 to 32. n ranges from 1 to 4. Phase shift Cyclone II PLLs have an advanced clock shift capability that enables programmable phase shifts in increments of at least 45°. The finest resolution of phase shifting is determined by the voltage control oscillator (VCO) period divided by 8 (for example, 1/1000 MHz/8 = down to 125-ps increments). Programmable duty cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each PLL post-scale counter (C0-C2). Number of internal clock outputs The Cyclone II PLL has three outputs which can drive the global clock network. One of these outputs (C2) can also drive a dedicated PLL<#>_OUT pin (single ended or differential). Number of external clock outputs The C2 output drives a dedicated PLL<#>_OUT pin. If the C2 output is not used to drive an external clock output, it can be used to drive the internal global clock network. The C2 output can concurrently drive the external clock output and internal global clock network. Manual clock switchover The Cyclone II PLLs support manual switchover of the reference clock through internal logic. This enables you to switch between two reference input clocks during user mode for applications that may require clock redundancy or support for clocks with two different frequencies. Gated lock signal The lock output indicates that there is a stable clock output signal in phase with the reference clock. Cyclone II PLLs include a programmable counter that holds the lock signal low for a user-selected number of input clock transitions, allowing the PLL to lock before enabling the locked signal. Either a gated locked signal or an ungated locked signal from the locked port can drive internal logic or an output pin. Clock feedback modes In zero delay buffer mode, the external clock output pin is phase-aligned with the clock input pin for zero delay. In normal mode, the PLL compensates for the internal global clock network delay from the input clock pin to the clock port of the IOE output registers or registers in the logic array. In no compensation mode, the PLL does not compensate for any clock networks. Control signals The pllenable signal enables and disables the PLLs. The areset signal resets/resynchronizes the inputs for each PLL. The pfdena signal controls the phase frequency detector (PFD) output with a programmable gate. |
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