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EP2C35A15F324C6N Datasheet(PDF) 33 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 33 Page - Altera Corporation |
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33 / 168 page  Altera Corporation 2–21 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture Global Clock Network The 16 or 8 global clock networks drive throughout the entire device. Dedicated clock pins (CLK[]), PLL outputs, the logic array, and dual-purpose clock (DPCLK[]) pins can also drive the global clock network. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, memory blocks, and embedded multipliers. The global clock lines can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin, or DQS signals for DDR SDRAM or QDRII SRAM interfaces. Internal logic can also drive the global clock network for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fan-out. Clock Control Block There is a clock control block for each global clock network available in Cyclone II devices. The clock control blocks are arranged on the device periphery and there are a maximum of 16 clock control blocks available per Cyclone II device. The larger Cyclone II devices (EP2C15 devices and larger) have 16 clock control blocks, four on each side of the device. The smaller Cyclone II devices (EP2C5 and EP2C8 devices) have eight clock control blocks, four on the left and right sides of the device. The control block has these functions: ■ Dynamic global clock network clock source selection ■ Dynamic enable/disable of the global clock network In Cyclone II devices, the dedicated CLK[] pins, PLL counter outputs, DPCLK[] pins, and internal logic can all feed the clock control block. The output from the clock control block in turn feeds the corresponding global clock network. The following sources can be inputs to a given clock control block: ■ Four clock pins on the same side as the clock control block ■ Three PLL clock outputs from a PLL ■ Four DPCLK pins (including CDPCLK pins) on the same side as the clock control block ■ Four internally-generated signals |
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